1. Field of the Invention
This invention relates generally to electronic circuits and, more particularly, to adjusting gain and offset mismatches in signal conditioning systems such as converter circuits.
2. Description of the Related Art
Interleaving is a well-known technique for achieving high sample rates in analog-to-digital converter (ADC) systems. An ADC converts an analog input signal into a digital output signal which represents the analog input signal in digital bits. In a typical implementation, an array of ADCs is arranged to sample the analog input signal in a sequential manner. If each ADC can be clocked at a frequency ƒc and if there are M ADCs, then the maximum effective sampling frequency ƒs for the interleaved system is ƒs=M·ƒc. It is desirable to increase the sampling frequency so that the analog input signal can be resolved more accurately. The resolution depends on the number of bits in the digital output signal used to represent the analog input signal.
Unfortunately, mismatches between interleaved ADCs can cause significant spurious tones or frequency components at the system's output. These mismatches can be caused by offset and gain mismatches which can affect the Signal-to-Noise and Distortion (SINAD) ratio. A larger SINAD ratio is desirable because it increases the dynamic range of the system so that smaller amplitude analog input signals can be detected accurately in the presence of noise. The dynamic range typically refers to the range of amplitudes between different input signals which can be reliably detected.
Several techniques have been used to reduce mismatches in interleaved ADCs. One technique is to cancel or compensate for the mismatch using an auxiliary input stage or capacitors. Examples of these techniques can be found in D. M. Hummels, J. J. McDonald and F. H. Irons, “Distortion compensation for time-interleaved analog-to-digital converters,” IEEE Instrument and Measurement Technology Conference, pp 728-731, June 1996, or C. S. G. Conroy, D. W. Cline and P. R. Gray, “An 8-b 85-MS/s Parallel Pipeline A/D Converter in 1-μm CMOS,” Institute of Electrical and Electronic Engineering Journal of Solid State Circuits, Vol. 28, No. 4, pgs. 447-454, April 1993.
Other techniques use a special calibration routine to determine the mismatch, either at startup or during operation. To determine the mismatch during operation, an estimate of the mismatches can be obtained by adding a calibration signal to the input signal which limits the dynamic range of the input signal. See for example, D. Fu, K. Dyer, S. Lewis and P. Hurst, “A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters,” Journal of Solid State Circuits, pgs. 1904-1911, December 1998, K. Dyer, D. Fu, S. Lewis and P. Hurst, “An Analog Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters,” Journal of Solid State Circuits, pgs. 1912-1919, December 1998, and L. Sumanen, M. Waltari and K. Halonen, “A 10-bit 200 MS/s CMOS Parallel Pipeline A/D Converter,” Journal of Solid State Circuits, pgs. 1048-1055, July 2001.
Another technique to reduce mismatches is to trim the ADCs during fabrication. However, trimming usually cannot correct for mismatches caused by temperature changes which occur during operation. Consequently, trimming during fabrication may not adequately reduce mismatches which change as a function of time.
Interleaved ADC systems can have offset mismatches or gain mismatches. For ADC offset mismatches, it may only be necessary to correct for the difference in offsets between ADCs. However, most offset correction solutions seek to detect the absolute offset of each ADC and then reduce the offset signal to zero. These solutions estimate the ADC offset signal by averaging the output of each ADC over a sufficiently long period of time because the offset error results in a shift in the average level of each output.
For these solutions to work accurately, however, the ADCs' input signal should have a zero dc component. Since most analog input signals have both ac and dc components, this can be problematic because the offset estimate will include both the dc component and the ADC offset signal. Hence, if the dc component is cancelled then the digital output signal will represent the ac component of the analog input signal without the dc component. Instead, the digital output signal should represent both the ac and dc components of the analog input signal. It should be noted that this simple averaging approach also cancels analog input signals at multiples of ƒc=ƒs/M which can further decrease the accuracy.
To avoid these problems, chopping techniques are commonly used when non-zero dc components are present in the analog input signal. A problem with using chopping, however, is that the same chopping techniques and circuitry typically do not work sufficiently for both a single ADC system and an interleaved ADC system. It is desired to be able to use the same chopping techniques and circuitry for both the single and interleaved ADC systems to make the design and fabrication of these systems simpler.
For a single ADC system, chopping separates the dc component from the ADC offset signal by first chopping or modulating the analog input signal by a tone or frequency at ƒs/2 so that the dc component is shifted to ƒc/2. After chopping, the remaining dc signal at the ADC output will mostly be from the ADC offset signal and not the dc component. Hence, a low-pass filter can be used to filter the output signal to obtain an estimate of the ADC offset signal.
For an interleaved ADC system, the situation is different. In these systems with M ADCs and a sampling rate ƒs, each sub-ADC's clock rate can be ƒc=ƒs/M. As a result when chopping is applied, input tones at i·ƒs/M (i=1, 2, . . . , M−1) will be aliased to dc where they will be indistinguishable from the offset component. The dc or average output is not a reliable estimate of the ADC's offset. Thus, a chopping circuit that can be used with a single ADC system may not be adequate for use with an interleaved ADC system. Because of this, the chopping circuitry used for a single ADC system is different than the chopping circuitry used for an interleaved ADC system.
Besides offset mismatches, gain mismatches are commonly found in interleaved ADC systems and can also cause a sequence of tones or frequencies at (i·ƒs/M)+or (i·ƒs/M−ƒin (i=1, 2 . . . M−1). Gain mismatches typically appear as deviations in the slope of the ADC's transfer function which can limit the ADC's dynamic range and SINAD. The dynamic range and SINAD can be improved by trimming the gain of each channel after fabrication or at some point during operation, but to enable the trim process, a reliable method of estimating the gain of each sub-ADC or the gain mismatch between a reference ADC and a sub-ADC is necessary.
Gain mismatches have typically been estimated in one of three ways, including running a separate calibration cycle, adding a calibration signal to the ADC's input signal, or assuming the input signal has certain characteristics. However, each of these techniques limit the usefulness of the interleaved ADCs to certain applications.
For example, in some interleaved ADC systems, a calibration routine with a known calibration signal such as a sine wave is applied to the ADCs input as disclosed in Hummels et al., then the sub-ADCs' outputs are analyzed in either the time or frequency domain. In the time domain, the relative size of each channel's output signal is determined. In the frequency domain, a Digital Fourier Transform is used to uncover frequencies at (i·ƒs/M)+ƒin or (i·ƒs/M)−ƒin (i=1, 2, . . . , M−1). The result of the time or frequency domain analysis is then used to provide an estimate of the gain mismatch. Unfortunately, in many applications, it is either difficult or inconvenient to provide some dead or unused time in which to run the calibration routine because the calculations can be intensive and time consuming.
To avoid the need for a separate calibration, one can add the calibration signal to the input signal as disclosed in Fu et al. Then, assuming the calibration and analog input signals are uncorrelated, the calibration signal is separated from the analog input signal and an estimate of the gain mismatch can be made as before. Unfortunately, the use of a calibration signal significantly reduces the allowable dynamic range of the analog input signal. The dynamic range is reduced because now the sum of the calibration signal and the analog input signal has to be within the dynamic range of the ADC.
The third approach to estimating the gain mismatch is to make assumptions about the characteristics of the analog input signal. Based on this, the gain mismatch between channels can be estimated. One problem with this approach is that the range of applications in which the approach works is restricted because the analog input signal is restricted to the assumed characteristics. If the analog input signal is outside the assumed dynamic range, then the gain mismatch estimation can be inaccurate.
Consequently, there is a need for a signal conditioning system which can adjust and correct offset and gain mismatches of both a single and interleaved ADC system. Further, there is a need for a signal conditioning system where the offset and gain mismatches can be corrected continuously without interrupting the processing of any incoming signals so that data can be processed with minimal delays.